Emacs Keyword Syntax Highlighting for Verilog, Specman Elite

/* Posted April 28th, 2008 at 4:04pm    */
/* Filed under Programming, Reference    */

/* */

If you’re an avid Unix user you’ve probably used Emacs at one point or another. Ever wonder how sometimes when you open up a file (like .cpp) the editor is able to highlight and color all the right keywords pertaining to the programming language the file is coded in? The secret is in the .emacs file located in your home directory. I’ve worked with both Verilog and Specman Elite files before, and found the correct code to add in the .emacs file to enable the beautiful keyword syntax highlighting/coloring that makes the code much more readable.

For Verilog, place this verilog-mode.el file in the “~/elisp” directory. If it does not exist, create it. Then copy and paste this in at the end of your .emacs file (because that’s the safest place to put your own customizations:

;;;;;; for verilog syntax highlighting ;;;;;;;
(defun prepend-path ( my-path )
(setq load-path (cons (expand-file-name my-path) load-path)))
(defun append-path ( my-path )
(setq load-path (append load-path (list (expand-file-name my-path)))))
;; Look first in the directory ~/bin for elisp files
(prepend-path "~/elisp")
;; Load verilog mode only when needed
(autoload 'verilog-mode "verilog-mode" "Verilog mode" t )
;; Any files that end in .v should be in verilog mode
(setq auto-mode-alist (cons '("\\.v\\'" . verilog-mode) auto-mode-alist))
;; Any files in verilog mode should have their keywords colorized
(add-hook 'verilog-mode-hook '(lambda () (font-lock-mode 1)))

For Specman Elite highlighting, place this specman-mode.el file in the “~/elisp” directory and then copy and paste this code into your .emacs file:

;;;;;; for specman e syntax highlighting ;;;;;;;
(defun prepend-path ( my-path )
(setq load-path (cons (expand-file-name my-path) load-path)))
(defun append-path ( my-path )
(setq load-path (append load-path (list (expand-file-name my-path)))))
;; Look first in the directory ~/elisp for elisp files
(prepend-path "~/elisp")
;; Load specman mode only when needed
(autoload 'specman-mode "specman-mode" "Specman mode" t )
;; Any files that end in .e, .e3, et cetera should be in specman mode
(setq auto-mode-alist
(append (list
(cons "\\.e\\'" 'specman-mode)
(cons "\\.e3\\'" 'specman-mode)
(cons "\\.load\\'" 'specman-mode)
(cons "\\.ecom\\'" 'specman-mode)
(cons "\\.etst\\'" 'specman-mode)) auto-mode-alist))
;; Any files in specman mode should have their keywords colorized
(add-hook 'specman-mode-hook '(lambda () (font-lock-mode 1)))

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7 Responses to “Emacs Keyword Syntax Highlighting for Verilog, Specman Elite”

  • Comment from leha

    Hi,
    I have downloaded specman.el file in elisp directory which is in my home & also pasted the specman code in my .emacs file. But still when I open some *.e file, the keywords are not highlighted…
    Any solution?

  • Comment from pil

    Enive seu tweet politicamente incorrento da frase q vc mais gosta do Tropa de Elite que vamos dar RT!!! #tropa2feelings

  • Comment from olascegnai

    They're all essentially the same truck, at the same price. Other than colour, the only real differentiation between them is that the third one has 10000 fewer miles on it.

    Unless you really like the chrome of the first one, or you see something on one or another of the trucks that indicates possible problems, I'd say the third one is the one you buy.

    Although personally, I prefer the 4 cyl 2.3L duratec engine to the V6.

  • Comment from baiger

    Aldec has trial verison for SV. try it.

    For

    Systemverilog tutorial
    Systemverilog randomization tutorial
    Systemverilog DPI tutorial
    Systemverilog Assertions tutorial
    Openvera tutorial
    Verification Concepts.
    Specman tutorial
    Verilog tutorial
    VMM tutorial
    RVM tutorial
    AVM tutorial
    OVM tutorial
    Verilog interview questions
    Specman interview questions
    Systemverilog interview questions
    OpenVera Interview questions

    Ckeckout http://www.testbench.in

  • Comment from mauri jakenbara

    Bristol – Superb new ASIC Verification opportunity for a senior level engineer. Required skills: ASIC / SoC verification, RTL design, HVLs such as e / SystemVerilog / Specman, pseudo-random verification, IO protocols such as USB and PCI, processor. This is a unique opportunity to join a pre-IPO company developing hardware and software to support a new architecture of processors. Due to ongoing success and d

  • Comment from uchi stasyant

    I measured 1.2 ahhs per 10 seconds.

  • Comment from obertelezi

    siang ini ketemuan sama verilog. hahahha


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